The building blocks of AI infrastructure: chips, networks, and training, explained simply

Welcome back to the OptimusEdge. There are now at least five different acronyms competing for the title of "the chip that runs AI" and most people using AI every day couldn't tell you what separates any of them, or how a pile of chips actually becomes something that can hold a conversation.
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Google's biggest chip cluster yet: The latest-generation TPU, codenamed Ironwood, can interconnect 9,216 chips in a single rack using Google's own optical circuit switch, a scale no other chip vendor currently matches.

Your next laptop needs a dedicated AI chip: Microsoft's Copilot+ PC standard now requires a minimum of 40 TOPS of NPU performance and 16GB of RAM on-device AI chips are quietly becoming a baseline spec, not a premium feature.

Everyone's building their own chip now: Beyond Google's TPU, Amazon (Trainium/Inferentia), Meta (MTIA), and Microsoft (Athena) are all designing custom AI silicon, no hyperscaler wants to depend entirely on one chip vendor anymore.

GPU (Graphics Processing Unit): the general-purpose workhorse. Originally built for video games, it turned out to be excellent at AI because both jobs need the same thing thousands of small calculations happening in parallel. Think of it as a Swiss Army knife: versatile, good at a lot, not perfectly optimized for any one task.

TPU (Tensor Processing Unit): Google's own chip, built specifically for the one math operation that dominates AI matrix multiplication. It's not a competitor category to GPU; it's technically a type of ASIC, and its first generation delivered 83x better performance-per-watt than a CPU and 29x better than a GPU for that one specific job.

ASIC (Application-Specific Integrated Circuit): the umbrella term for any chip custom-built for one job instead of general use. Every TPU is an ASIC. Not every ASIC is a TPU Amazon's Trainium and Meta's MTIA are both ASICs built for their own specific workloads, not sold to anyone else.

NPU (Neural Processing Unit): the small, efficient chip now built into your phone or laptop, dedicated purely to running AI locally rather than training it. NPUs are 40–60x more power-efficient than a GPU for that job, but they can only run models, not build them think screwdriver, not toolbox.

One chip is never enough for a real model which is where networking comes in (the topic we went deep on in issue #3). The short version: chips inside the same server talk over ultra-fast interconnects like NVLink, and chips across different servers talk over InfiniBand or Ethernet, which is meaningfully slower. That gap is why "how many GPUs do you have" is the wrong question how well they're connected matters just as much.

Raw compute becomes a usable model through three distinct stages. Pretraining is the biggest and most compute-hungry step: the model reads through 5–20 trillion tokens roughly every public book, paper, and code repository combined and just learns to predict the next word.

This produces a model that's fluent but not necessarily helpful or safe. Supervised fine-tuning (SFT) comes next: humans write example prompt-and-response pairs, and the model is trained to match that format this is what teaches it to actually follow instructions instead of just completing text.

Finally, RLHF (reinforcement learning from human feedback) ranks multiple model responses by quality and trains the model toward the ones humans preferred this is the stage that shapes tone, helpfulness, and what the model will and won't say. All three stages run on the same chips and network we just covered training is what those layers are actually built for.

Takeaway: The chip, the network connecting it to others, and the training process running on top of it aren't three separate topics they're the same pipeline, viewed from three different angles. Understanding one makes the other two make a lot more sense.

That's today's briefing. If someone on your team still uses "GPU" and "AI chip" interchangeably, this one's for them. Past issues are in the archive. See you tomorrow.

Epoch AI's Machine Learning Hardware Database: A free, continuously updated database comparing GPUs, TPUs, and other AI accelerators on real specs FLOPS, memory bandwidth, and release dates useful the next time a vendor pitch throws numbers at you without context.

Chip Fundamentals: GPU, NPU, TPU, LPU... How Many Types of "PUs" Are There in 2026? - the full processor family, including who builds what and why

ASIC vs. TPU Clarified: Global AI Hardware Landscape 2026 the direct answer to "is a TPU an ASIC"

Training Pipeline: Pre-training vs Fine-tuning vs RLHF What Each Stage Does a clear walkthrough of all three training stages

RLHF Deep Dive: What Is RLHF & How Does It Work? the process behind ChatGPT, Claude, and most conversational AI systems

That’s it for today !☀

Edge AI is levelling up are you? Until next time, stay curious, stay building, and don’t let your machines take over. 🤖😆

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Your Edge AI Explorer,
Sharat Sami (Let’s connect on LinkedIn)